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ICS650-36
Networking & PCI Clock Source
Description
The ICS650-36 is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal input of 25 MHz to produce four output clocks supporting LAN, PCI, and 100M SDRAM functions. The device also has a power down feature that tri-states the clock outputs and turns off the PLL when the PDTS pin is taken low.
Features
* * * * * * * * * *
Packaged in 16-pin TSSOP Available in Pb (lead) free package Replaces multiple crystals and oscillators Input crystal or clock frequency of 25 MHz Fixed reference output frequency of 25 MHz Selectable output frequencies of 33.3, 33.333, 50, 66.666, 100, and 125 MHz Duty cycle of 40/60 Operating voltage of 3.3 V Advanced, low-power CMOS process Industrial and commercial temperature ranges
Block Diagram
VDD 3
S2:0
3
Select/ Control Circuit
PLL1
CLK1
PLL2
CLK2
PLL3 X1/ICLK 25 MHz crystal input X2 Crystal Oscillator/ Clock Buffer
CLK3
REF
External capacitors may be required.
3 GND PDTS
(all outputs and PLLs)
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5 25 Race Street, San Jose, CA 9 5126
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ICS650-36 Networking & PCI Clock Source
Pin Assignment
X2 X1 GND CLK3 PDTS S2 CLK2 VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD GND REF S0 VDD CLK1 GND S1
CLK Output Selection Table
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 REF OFF ON ON ON ON ON ON ON CLK1 33.30 33.333 33.333 66.666 33.333 33.333 33.333 33.30 CLK2 50 33.333 66.666 66.666 50 50 66.666 50 CLK3 125 125 125 125 125 100 100 125
16-pin (173 mil) TSSOP
Note: All frequencies are in MHz.
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13
Pin Name
X2 X1 GND CLK3
Pin Type
Output Input Power Output
Pin Description
Crystal connection. Connect to 25 MHz crystal input or float for clock. Crystal connection. Connect to 25 MHz crystal or clock input. Connect to ground. Selectable clock output. See table above for frequency. Weak internal pull-down when tri-state. Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. Select pin. Selects clock output frequency from table above. Internal pull-up resistor. Selectable clock output. See table above for frequency. Weak internal pull-down when tri-state. Connect to +3.3 V. Select pin. Selects clock output frequency from table above. Internal pull-up resistor. Connect to ground. Selectable clock output. See table above for frequency. Weak internal pull-down when tri-state. Connect to +3.3 V. Select pin. Selects clock output frequency from table above. Internal pull-up resistor.
PDTS S2 CLK2 VDD S1 GND CLK1 VDD S0
Input Input Output Power Input Power Output Power Input
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ICS650-36 Networking & PCI Clock Source
Pin Number
14 15 16
Pin Name
REF GND VDD
Pin Type
Output Power Power
Pin Description
Reference 25 MHz clock output. Weak internal pull-down when tri-state. Connect to ground. Connect to +3.3 V.
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the ICS650-36 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between each VDD and the PCB ground plane. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2 = 20].
PCB Layout Recommendations
Observed the following guidelines for optimum device performance and lowest output phase noise: 1) The 0.01F decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) Place the 33 series termination resistor (if needed) close to the clock output to minimize EMI. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS650-36. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Series Termination Resistor
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
Crystal Load Capacitors
The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground.
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ICS650-36 Networking & PCI Clock Source
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-36. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Storage Temperature Junction Temperature Soldering Temperature -0.5 V to 7 V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -40 to +85C -65 to +150C 125C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Power Supply Voltage (measured in respect to GND)
Min.
0 -40 +3.135
Typ.
Max.
+70 +85
Units
C C V
+3.3
+3.465
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ICS650-36 Networking & PCI Clock Source
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85C
Parameter
Operating Voltage Supply Current Power Down Current Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Short Circuit Current Input Capacitance, inputs Nominal Output Impedance Internal Pull-up Resistor Internal Pull-down Resistor
Symbol
VDD IDD IDDPD VIH VIL VOH VOH VOL IOS CIN ZOUT RPU RPD
Conditions
No load, PDTS=1 No load, PDTS=0 PDTS, S2:0 PDTS, S2:0 IOH = -4 mA IOH = -12 mA IOL = 12 mA Clock outputs
Min.
3.135
Typ.
3.3 25 100
Max.
3.465
Units
V mA A V
2 0.8 VDD-0.3 2.4 0.4 65 5 20
V V V V mA pF k k
PDTS, S2:0 Outputs
500 250
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85C
Parameter
Input Frequency Output Rise Time Output Fall Time Output Clock Duty Cycle Absolute Clock Period Jitter Clock Jitter, Cycle-to-Cycle Clock Jitter, Long Term Frequency Synthesis Error Output Enable Time Output Disable Time
Symbol
fIN tOR tOF
Conditions
20% to 80%, Note 1 80% to 20%, Note 1 at VDD/2, Note 1 Note 1 33.333M, 66.666M, Note 1 25M, n=1000, Note1
Min.
Typ.
25 0.8 0.7
Max. Units
MHz ns ns 60 % ps ps ps ppm s ns
40 125 150 900 0 350 25
tOE tOD
PDTS high to output locked to 1% PDTS low to tri-state
Note 1: Measured with a 15 pF load.
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ICS650-36 Networking & PCI Clock Source
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
78 70 68 37
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
Marking Diagrams
(ICS650G-36)
16 9
(ICS650G-36LF)
16 9
650G-36 ###### YYWW$$
1 8
650G36LF ###### YYWW
1 8
(ICS650GI-36)
16 9
(ICS650GI-36LF)
16 9
650GI-36 ###### YYWW$$
1
Notes: 1. ###### is the lot code.
650GI36L ###### YYWW
1 8
8
2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. "LF" or "L" designates Pb free packaging. 4. "I" designates industrial temperature range. 5. Bottom marking: (origin). Origin = country of origin if not USA.
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ICS650-36 Networking & PCI Clock Source
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters Symbol Min Max
Inches* Min Max
E1 IN D EX AR EA
E
1
2
D
A A1 A2 b C D E E1 e L aaa
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004
A 2 A 1
A
*For reference only. Controlling dimensions in mm.
c
-Ce
b S E A T IN G P LA N E L
aaa C
Ordering Information
Part / Order Number
ICS650G-36 ICS650G-36T ICS650G-36LF ICS650G-36LFT ICS650GI-36 ICS650GI-36T ICS650GI-36LF ICS650GI-36LFT
Marking
(see page 6)
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel
Package
16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
(see page 6)
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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